S1C33L27 cmos 32-bit application specific controller 32-bit risc cpu-core (epson s1c33pe core) max.60mhz built-in 54kb ram (with cache, vram) built-in pll (multiplication rate: 1 to 16) built-in calculation module (calc) (multiply and accumulation (mac) matrix computation affine transformation butterfly computation and more) built-in lcd controller with 32kb ivram supports stn lcd panels with 4/8-bit data lines or tft lcd panels with up to 24-bit data lines. supports various panel resolutions, such as 640 480 pixels (vga) and 320 240 pixels (qvga) (can be configured according to the panel used). supports up to 16m-color (for color tft), 4k-color (for color stn), and 16-level gray scale (for monochrome stn) display modes. two-image overlay display via the pi cture-in-picture plus function interface to communicate with a built-in ram type lcd driver eight channels of table dma two channels of 16-bit audio pwm timer three channels of multi-serial interface that can be used as a uart, spi, or i2c module one channel of uart (conforms to irda 1.0.) general-purpose i2s audio bus interface with one input and one output channels resolution: 16 bits and 24 bits (pcm data output format) built-in infrared remote controller function mmc/sd/sdhc card interface support an edc (error detection c ode) and an ecc (error correction code) functions 8ch.(max) adc for analog input support usb interface with fifo isolated power supply boot function(nor/nand/spi/rs232c/hif) descriptions the S1C33L27 is a 32-bit application specif ic risc controller. it is suitable fo r applications that require an abundance of input/output ports and serial interfaces, usb, adc, and a display panel, such as electronic dictionaries and control panels on oa/fa equipment. the S1C33L27 incorporates an lcd contro ller and vram supporting qvga display in single-chip. adding an external sdram expands this capability into more higher reso lution and displayable colors (e.g., vga display, 16m-color display). it provides an interface to communicate with a built-in ram type lcd driver. ? features cpu ? epson original c33 pe 32-bit risc cpu-core ? maximum operating frequency: 60 mhz ? internal two-stage pipeline ? instruction set: 128 instructions (16-bit fixed length) internal memories ? a0ram (general-purpose ram) - 20k bytes (including 1k-byte instru ction cache and 1k-byte data cache) - usable as a general-purpose ram when not used as cache ram ? ivram (internal vram) - 32k bytes - configurable as a general-purpose ram in ar ea 0 or a ram for the calculation module ? dstram (dma descriptor table ram) - 2k bytes - configurable as a ram for the calculation module ? bbram (battery backup ram) - 16 bytes - the ram contents can be maintained while the system power is off using the separated power supply for rtc. input clock
S1C33L27 ? high-speed clock (osc3) - maximum input clock frequency: 48 mhz - generated by the oscillator circuit (using an external cr ystal or ceramic resonator) or an external clock is input. ? low-speed clock (osc1) - 32.768 khz (typ.) clock for rtc and low-power operations - generated by the oscillator circuit (using an external crystal resonator) or an external clock is input. cache controller (ccu) ? 1k-byte instruction cache and 1k-byte data ca che that adopts a four-w ay associative method ? lru replacement algorithm ? automatic lock function during debug mode and the interrupt process of specified priority ? write through function with a 1-word write buffer dma controller (dmac) ? eight channels of table dma ? supports table reloading and low-priority channel pausing functions. ? 24 hardware trigger sources and 8 software trigger sources sram controller (sramc) ? allows connection of sram , rom, and flash memories. ? 26-bit address bus and 8/16-bit selectable data bus ? up to six chip enable signals are av ailable to connect external devices. ? up to 64m-byte (a[25:0]) address space c an be accessible with each chip enable signal. ? programmable bus access wait cycle (0 to 15 cycles) ? little endian access ? memory mapped i/o ? supports both a0 and bs (bus strobe) type devices. ? supports external wait request via the #wait pin. sdram controller (sdramc) ? supports sdram interface. ? supports only sdram devices with 8/16-bit data bus. - minimum configuration: 16m bits (2mb), 16-bit sdram 1 - maximum configuration: 512m bits (64mb), 16-bit sdram 1 ? cas latency: one, two, or three programmable ? supports two-burst read and single write operations. ? equipped with a four-stage 16-bit dqb (data queue buffer). ? supports up to four sdram banks and bank active mode. ? built-in 12-bit auto-refresh counter ? intelligent self-refresh function for low power operation ? arbitrates external bus accesses by ahb-1 (cpu, dmac, hif) and ahb-2 (lcdc). host processor interface (hif) ? 8- or 16-bit asynchronous paralle l interface to control the s1c 33l27 by an external host processor ? provides semaphore registers. clock management unit/oscillators/pll (cmu) ? selects the system clock source (osc3, pll, or osc1). ? turns the osc3 and osc1 oscillator circuits on and off. ? controls frequency multiplication rate of the pll (1 to 16). ? controls clocks according to the standby mode (sleep and halt). ? controls the external clock. ? controls clock supply to the core and peripheral modules. ? osc3 oscillator circuit - crystal oscillation: 5 mhz min. to 48 mhz max. - ceramic oscillation: 5 mhz min. to 48 mhz max. - external clock input: 2 mhz min. to 48 mhz max. * a 48 mhz clock source with 0.25% of accuracy should be connected for using the usb function. * before using a ceramic resonator, please be sure to contact murata manufacturing co., ltd. for further information on conditions of use for ceramic resonators. ? pll - pll input frequency: 5 mhz min. to 48 mhz ma x. (osc3 1, 1/2, 1/3, ... 1/9, 1/10) - pll output frequency: 20 mhz min. to 60 mhz max. - multiplication rate: 1, 2, 3, ... 15, 16 ? osc1 oscillator circuit - crystal oscillation: 32.768 khz typ. - external clock input: 32.768 khz typ. interrupt controller (itc) ? five non-maskable interrupts ? 34 maskable interrupts (including four software exceptions) 16-bit audio pwm timer (t16p) ? two channels of 16-bit timer/counter with pwm output function ? three bit division modes are provided. (10 bits + 6 bits, 9 bits + 7 bits, 8 bits + 8 bits) ? can support 8, 16, 22.05, 32, 44.1, and 48 khz sampling rates. 2
S1C33L27 ? pwm function that can handle 8-bit and 16-bit pcm data with 8 k to 48 kbps sampling rates ? provides fine mode to improve the precision of the pulse width. ? supports a digital volume control function. ? can generate two types of compare-match interrupts. ? supports dma transfer. fine mode 8-bit timers (t8f) ? six channels of 8-bit timer with fine mode (presettable down counter) ? clocks generated with the counter underflow can be out put to internal devices (usi, usil, adc, and uart). ? each timer can generate underflow interrupts. 16-bit pwm timer (t16a6) ? four channels of 16-bit timer with a counter capture/comparison functions ? each channel has built-in two comparison/capture data buffers. ? can generate compare/capture interrupts. ? the counter clock can be selected from the sy stem clock, osc3 cl ock, and osc1 clock. ? supports dma transfer. watchdog timer (wdt) ? 30-bit watchdog timer to generate an nmi or a reset ? programmable watchdog timer overflow per iod (nmi or reset interrupt period) ? the watchdog timer overflow signal can be output outside the ic. real time clock (rtc) ? contains time counters (seconds, minutes, and hours) and calendar counters (day s, days of the week, months, and year). ? 24-hour or 12-hour mode can be selected. ? operates with an independent power supply (rtcvdd) separated from system power (operable while the system power is off). ? provides the wakeup output pin and #stb y input pin to control standby mode. ? can generate clock interrupts. universal serial interface (usi) ? three channels of multi-serial interface t hat can be used as a uart, spi, or i2c module ? contains 1-byte receive data buffer and 1-byte transmit data buffer. ? uart mode - character length: 7 or 8 bits - parity mode: even, odd, or no parity - stop bit: 1 or 2 bits (start bit: 1 bit fixed) - supports both msb first and lsb first modes. - parity error, framing error, and overrun error detectable - can generate receive buffer full, transmit buf fer empty, and receive error interrupts. - supports dma transfer. ? spi mode - supports both master and slave modes. - data length: 8 or 9 bits (master mode), 8 bits fixed (slave mode) - supports both msb first and lsb first modes. - data transfer timing (clock phase and polarity va riations) is selectable from among 4 types. - can generate receive buffer full, transmit buf fer empty, and overrun error interrupts. - supports dma transfer. ? i2c mode - supports both master (single master only) and slave modes. - 7-bit addressing mode (10-bit addressing is possible by software control.) - supports clock stretch/wait functions. - can generate start/stop, data transfer, ack/ nak transfer, and overrun error interrupts. universal serial interface with built-in ram lcd interface (usil) ? multi-serial interface that can be used as a ua rt, spi, i2c, or built-in ram lcd interface module ? contains 1-byte receive data buffer and 1-byte transmit data buffer. ? uart mode - same features as usi ? spi mode - data length: 8 bits fixed - other features are the same as usi. ? i2c mode - same features as usi ? lcd spi mode - data length is configurable for 8 bits, 16 bits, 18 bits (4 data format) and 24 bits + cmd bit. - cmd bit or a0 is selectable. - data transfer timing (clock phase and polarity va riations) is selectable from among 4 types. - can generate transmit buffer empty interrupts. - supports dma transfer. ? lcd parallel interface mode - provides 8-bit data bus, #cs, #rd, #wr and a0 control signals. seiko epson corporation 3
S1C33L27 - supports byte read/write access mode only. - can generate transmit buffer empty and receive buffer full interrupts. - supports dma transfer for both data transmission and reception. uart ? one channel of uart is available. ? conforms to irda 1.0. ? two-byte receive data buffer and one-byte transmit buffer are built in to support full-duplex communication. ? transfer rate: 150 to 460800 bps, character length: 7 or 8 bits, parity mode: even, odd, or no parity, stop bit: 1 or 2 bits ? parity error, framing error, and overrun error detectable ? can generate receive buffer full, transmit buffer empty, and receive error interrupts. i2s bus interface (i2s) ? general-purpose i2s audio bus interface with one input and one output channels ? contains a 24-byte fifo (24 bits 2 channels (l & r) 4). ? resolution: 16 bits and 24 bits (pcm data output format) ? clock polarity and data shift direction (msb fi rst/lsb first) are software configurable. ? can generate fifo empty interrupts for the output c hannel (half empty, whole empty, or one empty) and fifo full interrupts for the input channel (whole full or one data). ? supports dma transfer. card interface (card) ? generates 8-bit slc/mlc nand flash interface signals. ? includes a reed-solomon codec to support an edc (error detection code) and an ecc (error correction code) functions. ? a #ce area can be selected to connect a nand flash. mmc/sd/sdhc card interface (sd_mmc) ? sd/sdhc card controller compatible with sd memory card physical layer specification version 2.00. ? mmc controller compatible with multimedi acard system specification version 2.2. ? variable clock rate up to 30 mhz. ? supports 4-bit (wide bus) and 1-bit sd bus interface. ? crc7 and crc16 generators ? supports dma transfer. note : please join the sd association (sda) when handling sd and sdhc cards. infrared remote controller (remc) ? outputs a modulated carrier signal and inputs remote control pulses. ? embedded carrier signal generator and data length counter ? can generate counter underflow interrupts for dat a transmission and input rising/falling edge detection interrupts for data reception. lcd controller (lcdc) ? supports stn lcd panels with 4/8-bit data lines or tft lcd panels with up to 24-bit data lines. ? supports various panel resolutions, such as 640 480 pixels (vga) and 320 240 pixels (qvga) (can be configured according to the panel used). ? supports up to 16m-color (for color tft), 4k-color (f or color stn), and 16-level gray scale (for monochrome stn) display modes. ? typical display configuration when the internal vram (20kb) is used - 320 240 pixels, 2 bpp (4-level gray scale display) ? display configuration when an external memory is used - 320 240 pixels, 16 bpp (qvga 64k-colors display) - 400 240 pixels, 16 bpp (wqvga 64k-colors display) - 640 480 pixels, 16 bpp (vga 64k-colors display) ? two-image overlay display via the picture-in-picture plus function ? virtual display function to handle images with a differ ent resolution from the lcd panel (any area in the virtual screen can be displayed on the lcd.) a/d converter (adc10) ? 10-bit successive approximation type a/d converter ? up to eight analog input channels (chip and pfbga12u-180 package) ? up to four analog input channels (tqf p24/qfp20-144pin and tqfp15-128pin packages) ? conversion time: 10 s min. (when 2 mhz input clock is selected) 1,250 s max. (when 16 khz input clock is selected) ? can generate conversion completion and data overwrite error interrupts. usb function controller (usb) ? supports usb2.0 full speed (12m bps) mode. ? provides auto negotiation function. ? supports control, bulk, isoc hronous and interrupt transfers. ? supports four general-purpose endpoints and endpoint 0 (control). ? embedded 1k-byte programmable fifo ? can generate usb interrupts. ? supports dma transfer. general-purpose i/o ports (gpio) ? maximum 91 i/o ports and eight input ports are available (chip and pfbga12u-180 package). 4
S1C33L27 ? maximum 72 i/o ports and four input ports are available (tqfp24/qfp20-144pin package). ? maximum 56 i/o ports and four input ports are available (tqfp15-128pin package). ? can generate maximum 8 port input interrupts from the 64 i/o ports selected and key input interrupts from the predefined 32 ports. * the gpio ports are shared with other peripheral func tion pins (usi, pwm etc.). therefore, the number of gpio ports depends on the peripheral functions used. calculation module (calc) ? multiply and accumulation (mac) ? matrix computation ? affine transformation ? butterfly computation ? supports signed/unsigned 32-bit integer operation m ode and signed 16-bit fixed-point values operation mode with saturation processing. operating voltage ? hvdd (i/o power voltage) 2.7 v to 3.6 v (3.3 v typ.) or 3.0 v to 3.6 v (3.3 v typ.) when the usb module is used. ? avdd (analog power voltage) 2.7 v to 3.6 v (3.3 v typ.) ? lvdd (internal logic/internal memory power voltage) 1.65 v to 1.95 v (1.8 v typ.) or 1.7 v to 1.9 v (1.8 v typ.) when a ceramic resonator is used. ? pllvdd (pll power voltage) 1.65 v to 1.95 v (1.8 v typ.) or 1.7 v to 1.9 v (1.8 v typ.) when a ceramic resonator is used. ? rtcvdd (rtc/bbram power voltage) 1.65 v to 1.95 v (1.8 v typ.) or 1.7 v to 1.9 v (1.8 v typ.) when a ceramic resonator is used. * lvdd = pllvdd = rt cvdd, hvdd = avdd the S1C33L27 does not support 5 v tolerant i/o. operating temperatures ? -40 to 85c ? 0 to 70c when the usb module is used or when a ceramic resonator is used. power consumption (no i/o current is included.) ? during sleep: 2.3 a typ. when rtc is running. 1.0 a typ. when rtc is not used. ? during halt: 4.3 ma typ. when 48 mhz osc3 clock is used as the system clock, all peripheral clocks = off. ? during execution: 18 ma typ. when 48 mhz os c3 clock is used as the system clock, cpu is running, all peripheral clocks = off. * power consumption can be reduced by controlling the clocks through the clock management unit (cmu). shipping form ? die form: 200 pads (5.213 mm 5.213 mm, pad pitch: 90 m) ? plastic package: tqfp15-128pin (14 mm 14 mm 1.0 mm, lead pitch: 0.4 mm) tqfp24-144pin (16 mm 16 mm 1.0 mm, lead pitch: 0.4 mm) qfp20-144pin (20 mm 20 mm 1.4 mm, lead pitch: 0.5 mm) pfbga12u-180 (12 mm 12 mm 1.2 mm, ball pitch: 0.8 mm) seiko epson corporation 5
S1C33L27 ? block diagram c33 pe core hif dm ac ccu cal c lcdc a0r am _i (8k bytes) a0r am _d (12k bytes) ir am (32k byt es) area 0 ivr am (32k byt es) sapb br id ge dstram (2k bytes) sram c sdramc bus controller misc cm u it c gpio pmux usi (3 ch ) usil u art usb psc wdt t8f (6ch) t16a (4ch) t16p (2ch) a dc10 i2s rem c card mmc lc dc (reg.) dm ac (reg.) sdramc (reg.) sr am c (reg.) ccu (reg.) hif (reg.) rtc bbram (16 byt es) arb iter ivram i/f external host proces sor ahb-1 ahb-2 external bus rtcv dd sapb soft ware switch S1C33L27 c33 pe core hif dm ac ccu cal c lcdc a0r am _i (8k bytes) a0r am _d (12k bytes) ir am (32k byt es) area 0 ivr am (32k byt es) sapb br id ge dstram (2k bytes) sram c sdramc bus controller misc cm u it c gpio pmux usi (3 ch ) usil u art usb psc wdt t8f (6ch) t16a (4ch) t16p (2ch) a dc10 i2s rem c card mmc lc dc (reg.) dm ac (reg.) sdramc (reg.) sr am c (reg.) ccu (reg.) hif (reg.) rtc bbram (16 byt es) arb iter ivram i/f external host proces sor ahb-1 ahb-2 external bus rtcv dd sapb soft ware switch S1C33L27 6
S1C33L27 notice: no part of this material may be reproduced or duplicated in any fo rm or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. se iko epson does not assume any liability of a ny kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, furt her, there is no representation that this material is app licable to products requiring high level reliab ility, such as, medical products. moreo ver, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that any thing made in accordance with this material will be free from any patent or copy right infringement of a third party. this material or portions thereof may contain technology or the subject relati ng to strategic products under the control of the foreign exchange and foreign trade la w of japan and may require an export license from the ministry of economy, trade and industry or other approval from another government ag ency. all brands or product names mentioned herein are trademarks and/ or registered trademarks of t heir respective companies. ? seiko epson corporation 2010, all rights reserved epson semiconductor website microdevices operations division device sales & marketing department 421-8 hino, hino-shi, tokyo 191-8501, japan phone: +81-42-587-5814 fax: +81-42-587-5117 http://www.epson.jp/device/semicon_e/ document code: 412051100 first issue dec, 2010
|
